What is multiplexer and demultiplexer pdf

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Carousel Previous Carousel Next. Jump to Page. Search inside document. Yap Uen Hsieh. Ahmad Nazrin. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal, that means it will perform the required operation when it is low.

Multiplexers 5. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line.

So we can say that a binary encoder, is a multi-input combinational logic circuit that converts the logic level "1" data at its inputs into an equivalent binary code at its output. Generally, digital encoders produce outputs of 2-bit, 3-bit or 4- bit codes depending upon the number of data input lines. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and to-4 line configurations.

The output lines of a digital encoder generate the binary equivalent of the input line whose value is equal to "1" and are available to encode either a decimal or hexadecimal input pattern to typically a binary or B. Also, an output code of all logic "0"s can be generated when all of its inputs are at "0" OR when input D0 is equal to one. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder for short.

The Priority Encoder solves the problems mentioned above by allocating a priority level to each input. The priority encoders output corresponds to the currently active input which has the highest priority. So when an input with a higher priority is present, all other inputs with a lower priority will be ignored. The priority encoder comes in many different forms with an example of an 8-input priority encoder along with its truth table shown below.

Priority Encoder Digital Encoder using Logic Gates Let the 16x1 Multiplexer has sixteen data inputs I 15 to I 0 , four selection lines s 3 to s 0 and one output Y. The Truth table of 16x1 Multiplexer is shown below. We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The block diagram of 16x1 Multiplexer is shown in the following figure. The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage.

The other selection line, s 3 is applied to 2x1 Multiplexer. Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one 16x1 Multiplexer. Gowthami Swarna. Asif Hussain. John Shea.

Raghu Pandey. The block diagram of 1x8 De-Multiplexer is shown in the following figure. The other selection line, s 2 is applied to 1x2 De-Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection lines and eight outputs.

Whereas, 1x16 De-Multiplexer has single input, four selection lines and sixteen outputs. So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen outputs. Input of this 1x2 De-Multiplexer will be the overall input of 1x16 De-Multiplexer. The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is shown in the following figure. The other selection line, s 3 is applied to 1x2 De-Multiplexer. Gowthami Swarna. Asif Hussain.